Chouliaras, Vassilios Koutsomyti, Konstantia Parr, Simon R. Mulvaney, David Milward, Mark J. Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: a case study in telephony workloads This research discusses hardware architectures, script-based automation and software and hardware methodologies for developing customized System-on-Chip scalar/vector processors within the example application domain of telephony codes. The approaches researched include Register-Transfer-Level methodologies resulting in an SIMD-enhanced processor known as the ITU-VE1, and Electronic System Level methodologies resulting in a multi-parallel vector processor known as the SS-SPARC. The example applications were the ITU-T G.729A and G.723.1 speech codecs chosen for their abundant data-level parallelism and availability for research purposes. Results indicate the proposed scalar/vector accelerators achieve a maximum speed-up of 4.27 and 4.62 for the G729.A and G723.1 encoders respectively for 512-bit wide SIMD configurations. Both vector processors resulting from the proposed methodologies were implemented as VLSI macros and compared at the silicon level. Compared to the Register-Transfer-Level flow, the Electronic System Level flow implementing the same datapath results in increased power consumption of 3-15% however delivers an area reduction of 2-18% and substantially shortens design and verification time making it a viable alternative to established RTL methodologies. VLSI;Microprocessors;Vector processors;System-on-Chip (SoC);Electronic System Level (ESL) design;Mechanical Engineering not elsewhere classified 2016-09-16
    https://repository.lboro.ac.uk/articles/journal_contribution/Architecture_performance_modeling_and_VLSI_implementation_methodologies_for_ASIC_vector_processors_a_case_study_in_telephony_workloads/9547388