Investigations into hardware-based parallel lossless data compression systems

The current increases in silicon logic densities have made feasible the implementation of multiprocessor systems onto a single chip able to meet the intensive data processing demands of highly concurrent systems. This thesis describes research into a hardware implementation of a high performance parallel multi compressor chip. In order to fully explore the design space, several models are created at various levels of abstraction to capture the full characteristics of the architecture. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade-offs that affect compression performance, latency, and throughput. The most promising approach is written in a hardware description language and synthesised for FPGA hardware as proof of concept. It is shown that a multi compressor architecture can be a scalable solution with the ability to operate at throughputs to cope with the demands of modern high-bandwidth applications whilst retaining good compression performance.