New product designs within the electronics packaging industry
continue to demand interconnects at microscopic geometry, both
at the Integrated Circuit (IC) and supporting board level, thereby
creating numerous manufacturing challenges. Flip Chip On
Board (FCOB) applications are currently being driven by
competitive manufacturing costs and the need for higher volume
and robust production capabilities. One of today’s low cost
FCOB solutions has emerged as an extension of the existing
infrastructure for Surface Mount Technology (SMT) and
combines an Under Bump Metallisation (UBM) with a stencil
printing solder bumping process, to generate mechanically robust
joint structures with low electrical resistance between chip and
board. Although electroless Ni plating of the UBM, and stencil
printing for solder paste deposition, have been widely used in
commercial industrial applications, there still exists a number of
technical issues related to these materials and processes as the
joint geometry is further reduced. This paper reports on trials
with electroless Ni plating and stencil paste printing and the
correlation between process variables in the formation of bumps
and the shear strength of such bumps at different geometries. The
effect of precise control of the tolerances of squeegees, stencils
and wafer fixtures was examined to enable the optimisation of
the materials, processes and tooling for reduction of bumping
defects.
History
School
Mechanical, Electrical and Manufacturing Engineering
Citation
LIU, C....et al., 2004. Materials and processes issues in fine pitch eutectic solder flip chip interconnection. IN: Proceeding of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, (HDP '04). 30 June-3 July, Shanghai, China, pp.213-220.