RC71.pdf (942.67 kB)
Modeling of the power cycling performance of a Si on Si flip chip assembly
conference contributionposted on 2009-02-11, 16:25 authored by Andrew R. Ochana, David HuttDavid Hutt, David Whalley, Farhad Sarvar, A. Al-Habaibeh
Flip Chip (FC) technology offers many advantages over conventional surface mount technology, including a smaller device footprint and higher interconnection density. Low power but complex consumer items, such as mobile telecommunications devices, utilise this packaging technology and it is likely to spread to other electronics sectors where components have higher power dissipations and/or they have to operate in a hostile environment. As the scope for FC packaging broadens, a reliable means of establishing the long term performance of a particular package is necessary. Traditionally thermal cycling has been a primary reliability test for electronic assemblies including FC, however this fails to capture the behaviour of assemblies where the component thermal expansion is well matched to that of the substrate due to the isothermal heating and cooling of the assembly. In this situation power cycling offers an alternative means of determining the module performance.
- Mechanical, Electrical and Manufacturing Engineering
CitationOCHANA, A.R. ....et al., 2006. Modeling of the power cycling performance of a Si on Si flip chip assembly. IN: Proceedings of the Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems, (ITHERM '06), May 30 -June 2, San Diego, CA , pp. 243 - 250.
- VoR (Version of Record)
NotesThis is a conference paper [© IEEE]. It is also available at: http://ieeexplore.ieee.org/ Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.