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Download fileModeling of the power cycling performance of a Si on Si flip chip assembly
conference contribution
posted on 2009-02-11, 16:25 authored by Andrew R. Ochana, David HuttDavid Hutt, David Whalley, Farhad Sarvar, A. Al-HabaibehFlip Chip (FC) technology offers many advantages over
conventional surface mount technology, including a smaller
device footprint and higher interconnection density. Low
power but complex consumer items, such as mobile
telecommunications devices, utilise this packaging
technology and it is likely to spread to other electronics
sectors where components have higher power dissipations
and/or they have to operate in a hostile environment.
As the scope for FC packaging broadens, a reliable means of
establishing the long term performance of a particular
package is necessary. Traditionally thermal cycling has been
a primary reliability test for electronic assemblies including
FC, however this fails to capture the behaviour of assemblies
where the component thermal expansion is well matched to
that of the substrate due to the isothermal heating and cooling
of the assembly. In this situation power cycling offers an
alternative means of determining the module performance.
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