Parametric data-parallel architectures for TLM acceleration
conference contribution
posted on 2010-05-10, 09:18 authored by Vassilios Chouliaras, James FlintJames Flint, Yibin LiWe discuss the architecture and
microarchitecture of a scalable, parametric vector
accelerator for the TLM algorithm. Architecture-level
experimentation demonstrates an order of
magnitude complexity reduction for vector
lengths of 16 32-bit single-precision elements. We
envisage the proposed architecture replicated in a
SOC environment thus, forming a multiprocessor
system capable of tapping parallelism at the
thread level as well as the data level.
History
School
- Mechanical, Electrical and Manufacturing Engineering
Citation
CHOULIARAS, V.A., FLINT, J.A. and LI, Y., 2004. Parametric data-parallel architectures for TLM acceleration. IN: Proceedings of 3rd International Conference on Computational Electromagnetics and Its Applications (ICCEA 2004), Beijing, China, 1-4 November, pp. 569-572.Publisher
© IEEEVersion
- VoR (Version of Record)
Publication date
2004Notes
This is a conference paper [© IEEE]. It is also available from: http://ieeexplore.ieee.org/. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.ISBN
0780385624Language
- en
