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Parametric data-parallel architectures for TLM acceleration

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conference contribution
posted on 10.05.2010, 09:18 by Vassilios Chouliaras, James FlintJames Flint, Yibin Li
We discuss the architecture and microarchitecture of a scalable, parametric vector accelerator for the TLM algorithm. Architecture-level experimentation demonstrates an order of magnitude complexity reduction for vector lengths of 16 32-bit single-precision elements. We envisage the proposed architecture replicated in a SOC environment thus, forming a multiprocessor system capable of tapping parallelism at the thread level as well as the data level.

History

School

  • Mechanical, Electrical and Manufacturing Engineering

Citation

CHOULIARAS, V.A., FLINT, J.A. and LI, Y., 2004. Parametric data-parallel architectures for TLM acceleration. IN: Proceedings of 3rd International Conference on Computational Electromagnetics and Its Applications (ICCEA 2004), Beijing, China, 1-4 November, pp. 569-572.

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© IEEE

Version

VoR (Version of Record)

Publication date

2004

Notes

This is a conference paper [© IEEE]. It is also available from: http://ieeexplore.ieee.org/. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

ISBN

0780385624

Language

en

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