Parametric data-parallel architectures for TLM acceleration
conference contributionposted on 10.05.2010, 09:18 by Vassilios Chouliaras, James FlintJames Flint, Yibin Li
We discuss the architecture and microarchitecture of a scalable, parametric vector accelerator for the TLM algorithm. Architecture-level experimentation demonstrates an order of magnitude complexity reduction for vector lengths of 16 32-bit single-precision elements. We envisage the proposed architecture replicated in a SOC environment thus, forming a multiprocessor system capable of tapping parallelism at the thread level as well as the data level.
- Mechanical, Electrical and Manufacturing Engineering