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Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking

conference contribution
posted on 10.06.2015, 09:02 by Zhiheng Huang, Paul ConwayPaul Conway
Geometric scaling of the conventional silicon MOSFET following Moore’s law down to the 14nm or even lower dimension technology node presents many fundamental challenges. Therefore, three-dimensional integrated circuit (3-D IC) architectures emerge as a game changer to the continuation of the Moore’s law. Staking multiple chips by the through-silicon-vias and microbumps has been proved to be a viable technology. However, 3-D ICs are facing challenges in design, materials and reliability issues. This paper introduces a microstructure-based multiphysics modeling platform that integrates multiscale microstructural evolution modeling, quantification of microstructural features, and modeling of microstructure-level responses of the 3-D interconnects under thermal, mechanical and electrical fields. Multiscale microstructures formed in the interconnects during processes of solidification, aging, and electromigration under effects from geometries and external stresses are presented first. Different methods such as singular value decomposition (SVD), wavelet multi-resolution analysis, and radon transformation are then used to quantification of the microstructural characteristics in 3-D interconnects. Based on the quantified microstructural index, an effort to establish a microstructure-interconnect performance relationship is introduced. Finally, the response of microstructure under multiphysics fields and its implications to design reliable 3-D interconnects are discussed.


National Natural Science Foundation of China (NSFC) [grant no. 51004118]; Pearl River Nova Program of Guangzhou [grant no. 2012J2200074].



  • Mechanical, Electrical and Manufacturing Engineering

Published in

International Stress Workshop


HUANG, Z. and CONWAY, P.P., 2014. Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking. Presented at: International Stress Workshop, Austin, Texas, USA, 15-17 October 2014.


AM (Accepted Manuscript)

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Closed access. Keynote presentation from the International Stress Workshop




Austin,. Tx, USA

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