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An efficient multiple precision floating-point Multiply-Add Fused unit
journal contribution
posted on 2016-03-10, 14:26 authored by K. Manolopoulos, D. Reisis, Vassilios ChouliarasMultiply-Add Fused (MAF) units play a key role in the processor's performance for a variety of applications. The objective of this paper is to present a multi-functional, multiple precision floating-point Multiply-Add Fused (MAF) unit. The proposed MAF is reconfigurable and able to execute a quadruple precision MAF instruction, or two double precision instructions, or four single precision instructions in parallel. The MAF architecture features a dual-path organization reducing the latency of the floating-point add (FADD) instruction and utilizes the minimum number of operating components to keep the area low. The proposed MAF design was implemented on a 65 nm silicon process achieving a maximum operating frequency of 293.5 MHz at 381 mW power.
History
School
- Mechanical, Electrical and Manufacturing Engineering
Published in
Microelectronics JournalVolume
49Pages
10 - 18Citation
MANOLOPOULOS, K., REISIS, D. and CHOULIARAS, V.A., 2016. An efficient multiple precision floating-point Multiply-Add Fused unit. Microelectronics Journal, 49, pp. 10 - 18Publisher
© ElsevierVersion
- AM (Accepted Manuscript)
Publisher statement
This work is made available according to the conditions of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) licence. Full details of this licence are available at: https://creativecommons.org/licenses/by-nc-nd/4.0/Publication date
2016-01-04Notes
This paper was accepted for publication in the journal Microelectronics Journal and the definitive published version is available at http://dx.doi.org/10.1016/j.mejo.2015.10.012.ISSN
0026-2692Publisher version
Language
- en