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Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: a case study in telephony workloads

journal contribution
posted on 16.09.2016 by Vassilios Chouliaras, Konstantia Koutsomyti, Simon R. Parr, David Mulvaney, Mark J. Milward
This research discusses hardware architectures, script-based automation and software and hardware methodologies for developing customized System-on-Chip scalar/vector processors within the example application domain of telephony codes. The approaches researched include Register-Transfer-Level methodologies resulting in an SIMD-enhanced processor known as the ITU-VE1, and Electronic System Level methodologies resulting in a multi-parallel vector processor known as the SS-SPARC. The example applications were the ITU-T G.729A and G.723.1 speech codecs chosen for their abundant data-level parallelism and availability for research purposes. Results indicate the proposed scalar/vector accelerators achieve a maximum speed-up of 4.27 and 4.62 for the G729.A and G723.1 encoders respectively for 512-bit wide SIMD configurations. Both vector processors resulting from the proposed methodologies were implemented as VLSI macros and compared at the silicon level. Compared to the Register-Transfer-Level flow, the Electronic System Level flow implementing the same datapath results in increased power consumption of 3-15% however delivers an area reduction of 2-18% and substantially shortens design and verification time making it a viable alternative to established RTL methodologies.

Funding

This research was supported by EPSRC Grant GR/S44976/01.

History

School

  • Mechanical, Electrical and Manufacturing Engineering

Published in

Microprocessors and Microsystems

Volume

37

Issue

8 PARTD

Pages

1122 - 1143

Citation

CHOULIARAS, V. ... et al., 2013. Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: a case study in telephony workloads. Microprocessors and Microsystems, 37 (8D), pp.1122-1143.

Publisher

© Elsevier

Version

VoR (Version of Record)

Publisher statement

This work is made available according to the conditions of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) licence. Full details of this licence are available at: https://creativecommons.org/licenses/by-nc-nd/4.0/

Publication date

2013

Notes

Closed access.

ISSN

0141-9331

Language

en

Exports