FlxVRM: Enabling online configuring memory via virtualization on programmable data plane

<p dir="ltr">Programmable data plane (PDP) has emerged as a powerful platform for line-rate packet processing, utilizing on-chip register memory to execute stateful applications. Yet most existing efforts concentrate on static approaches for allocating register memory, necessitating switch restarting and service interruption. Despite the availability of research on sharing memory for concurrent applications, the rigid requirement of limiting memory sharing to the same pipeline stages hampers application flexibility and poses scalability challenges. To address this limitation, we present FlxVRM, a flexible register memory virtualization layer for data plane P4 programs which supports high-flexibility sharing of register memory for concurrent applications on PDP. FlxVRM enables memory allocation at any stage and location of the pipeline on PDP for each application at run time. To reduce resource usage during virtualization in the data plane pipeline, FlxVRM further merges different tables and actions with similar structures within P4 programs. Additionally, FlxVRM provides a compiler to generate data plane programs for virtualization as well as the control plane API configuration. A prototype of FlxVRM is implemented based on P4 hardware switches with Intel Tofino ASIC. Our experiment results show that FlxVRM significantly improves the allocatable memory space for applications by up to 50%, while reducing the resource of the table up to 68%.</p>