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Study of the effects of SEU-induced faults on a pipeline protected microprocessor

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posted on 30.04.2010, 13:27 by E. Touloupis, James FlintJames Flint, Vassilios Chouliaras, D.D. Ward
This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.

History

School

  • Mechanical, Electrical and Manufacturing Engineering

Citation

TOULOUPIS, E.....et al., 2007. Study of the effects of SEU-induced faults on a pipeline protected microprocessor. IEEE Transactions on Computers, 56(12), pp. 1585 - 1596

Publisher

© IEEE

Version

VoR (Version of Record)

Publication date

2007

Notes

This is a journal paper published in IEEE Transactions on Computers[© IEEE]. It is also available at: http://ieeexplore.ieee.org/ Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

ISSN

0018-9340

Language

en