A fault tolerant micoarchitecure for safety-related automotive control

The successful use of fly-by-wire systems in aviation along with the positive experience of drive-by-wire systems with mechanical backup for braking and power steering have led to the development of complete drive-by-wire systems that reduce the cost of a vehicle, are lighter and provide better passive safety to the passenger. These systems have the form of a distributed, real-time embedded system. Similar architectures can be found in other safetycritical and mission-critical applications in avionics, as mentioned before, medical equipment, and the industrial sector. The advances in embedded system technology has enabled designers to implement low-cost and small form factor electronics. However shrinking CMOS technologies are facing considerable reliability problems since they become more sensitive to transient faults. This thesis investigates the application of traditional methods for the development of safety critical computer systems and their application on single-chip devices. The contributions of this work are briefly summarised as follows: • The development of a novel fault-tolerant architecture for protecting the processor core. • Methods for performing fault-injection experiments on embedded processor architectures. • Fault-models for multiple faults on digital systems with the use of statistical distributions. • An extensive study of a processor's behaviour under the presence of faults within its pipelined execution unit.