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Electromigration time-to-failure analysis using a lumped element model

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thesis
posted on 02.07.2018 by Wan S. Wan Ismail
This thesis presents a theoretical and computer simulation of electromigration behaviour in the Integrated Circuit (IC) interconnection, with a particular emphasis on the analysis of the time-to-failure (TTF) produced through the Lumped Element model. The current and most accepted physical model for electromigration is the Stress Evolution Model which forms the basis for the development of the current Lumped Element Model. For early failures, and ignoring transport through the grain bulk, the problem reduces to that of solving the equations for stress evolution equation on the complex grain boundary networks which make the cluster sections of the near-bamboo interconnect. The present research attempts to show that the stress evolution in a grain boundary cluster network mimics the time development of the voltage on an equivalent, lumped CRC electrical network. [Continues.]

Funding

Standards and Industrial Research Institute of Malaysia (SIRIM Berhad).

History

School

  • Mechanical, Electrical and Manufacturing Engineering

Publisher

© Wan Sazaley Wan Ismail

Publisher statement

This work is made available according to the conditions of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) licence. Full details of this licence are available at: https://creativecommons.org/licenses/by-nc-nd/4.0/

Publication date

2001

Notes

A Doctoral Thesis. Submitted in partial fulfilment of the requirements for the award of Doctor of Philosophy at Loughborough University.

Language

en

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