Exploitation of thread- and data-parallelism in video coding algorithms

MPEG-2, MPEG-4 and H.264 are currently the most popular video coding algorithms for consumer devices. The complexity and computational intensity of their respective encoding processes and the associated power consumption currently limits their full deployment in portable or cost-sensitive consumer devices. This thesis takes two approaches in addressing these performance issues. Firstly in the static partitioning of application's control-flow-graphs using thread-level parallelism to share the computational load between multiple processors in a System-on-Chip multiprocessor configuration. Secondly, two separate design methodologies, one founded in RTL and in the second SystemC, were applied in order to investigate dedicated vector architectures in the acceleration of video encoding through the exploitation of data-level parallel techniques. By implementing two vector datapaths, one from each methodology, a comparison of the two is made. The key contributions of the work are summarised below: (1) demonstration of the reduction in computational workload per processor by exploiting thread-level parallelism; (2) static partitioning of three state-of-the-art video encoders, namely MPEG-2, MPEG-4 and H.264, to permit their execution on a multi-processor environment; (3) design of a vector datapath to accelerate MPEG-4 video encoding by implementing data-level parallelism; (4) comparative study of the potential of the ESL language, SystemC, in the design methodology, in comparison with the RTL.