Fault tree synthesis for real time and design applications on process plant

A method of fault tree synthesis relevant to the generation of fault trees for use both in hazard assessment in the design of plant and in the analysis of fault conditions using a process control computer is described. List processing techniques and bit manipulation have been used to reduce computation time and computer storage require ments. The programming language used in the development of the algorithm was RTL/2. Several examples are presented to illustrate the methodology.