High-performance load/store unit for a highly configurable, embedded vector processor

Voice-over-Internet-Protocol (VoIP) has gained a significant amount of interest due to insatiable demand for improved digital communication in the consumer market. Instead of using the traditional public exchange network telephone companies are now able to offer cheap telephone calls via the internet. The intention of this research is to improve the channel capacity of VoIP networks by researching a novel embedded CPU architecture for accelerating speech coding algorithms. The proposed architecture is a configurable vector coprocessor, closely coupled to a controlling Spare-VS compliant CPU. The design is developed as a System-on-Chip (SoC) component utilising high-performance connectivity. Two speech codecs, provided by the International Telecommunication Union (ITU) and usually found in VoIP applications are the primary workloads studied in this research. By implementing data-level-parallel hardware in the form of custom vector and scalar instructions, the benefit of data-level-parallelism is investigated. The vector instructions are designed to accelerate the inner-loops of the two speech algorithms and results are obtained over a range of vector lengths and different test vectors, provided by the ITU. The final section of this research is the design of a configurable vector Load/Store Unit (LSU). This was implemented at Register Transfer Level (RTL) Very High Speed Integrated Circuit Hardware Description Language (VHDL) and is included in the overall design of the vector coprocessor. Different configurations of the LSU were explored to give the cycle, area and power results across a number of speech workloads.