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Exploiting memory allocations in clusterized many-core architectures

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posted on 28.02.2019, 13:55 by Rafael Garibotti, Ost Copello-OstOst Copello-Ost, Anastasiia Butko, Ricardo Reis, Abdoulaye Gamatie, Gilles Sassatelli
Power-efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterization is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e., memory latency problems). This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on-chip mapped data in clusterized many-core architectures. First, this work reviews the current literature on memory allocations and explore the limitations of cluster-based many-core architectures. Then, several memory allocations are introduced and benchmarked scalability, performance and energy-wise, compared to the conventional centralized shared memory solution to reveal which memory allocation is the most appropriate for future mobile architectures. Our results show that distributed shared memory allocations bring performance gains and opportunities to reduce energy consumption.

History

School

  • Mechanical, Electrical and Manufacturing Engineering

Published in

IET Computers & Digital Techniques

Citation

GARIBOTTI, R. ... et al., 2019. Exploiting memory allocations in clusterized many-core architectures. IET Computers & Digital Techniques, 13 (4), pp.302-311.

Publisher

© Institution of Engineering and Technology (IET)

Version

AM (Accepted Manuscript)

Publisher statement

This work is made available according to the conditions of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) licence. Full details of this licence are available at: https://creativecommons.org/licenses/by-nc-nd/4.0/

Acceptance date

21/01/2019

Publication date

2019-01-22

Notes

This paper is a postprint of a paper submitted to and accepted for publication in IET Computers & Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library

ISSN

1751-8601

eISSN

1751-861X

Language

en

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